Multilayer circuit boards were developed to overcome area limitations associated with single-layered circuit boards. A multilayer circuit board can be either single- or double-sided, and may comprise multiple signal layers on the surface of and buried within the board. Such multilayer circuit boards have allowed a significant increase in the number of electrical signals that may be routed between electronic components mounted on the same circuit board. Thus, electronic components with a large number of input/output (I/O) pins may be mounted on a single circuit board. And sophisticated micro-systems may be delivered in multi-chip packages.
As the number of pin-outs increases, often accompanied by a decrease in pin pitch, it has become more and more difficult to achieve full power and ground flooding within a package. For example, due to high pin density, space limitations can make it impossible to route a trace to a power/ground pin. Even if a trace may be routed for a power/ground connection, it is often too thin for sufficient current to flow through. A high-density package also tends to have more severe electromagnetic interference (EMI) among its components. Sufficient ground flooding of the package is usually crucial to an effective containment of EMI.
Furthermore, high-density packages with multilayer circuit boards can produce a substantial amount of heat even during normal operations. Excessive heat tends to deteriorate the performance of electronic components and shorten their lifetime. Therefore, preventative measures become necessary to help dissipate excessive heat. However, space limitations within a multilayer circuit board often hinders the implementation of heat-dissipating measures.
Referring to FIG. 1, there is shown a layout footprint of a surface mount grid array package having over two hundred I/O contacts. FIG. 1 also shows a legend indicating the type of signal associated with each I/O contact. These I/O contacts may be accommodated by corresponding vias extending into or through the multilayer circuit board. As shown, while some of the ground vias are clustered in the center, others are loosely scattered throughout the layout footprint.
One prior art solution for providing ground flooding for the ground vias is illustrated in FIGS. 2 and 3. By applying the channel-routing techniques (e.g., dog-boning and power-sharing) described in earlier related patent applications, some vias may be re-arranged or removed, thereby creating via-free areas 202 and via-free channels 204 as illustrated in FIG. 2. Then, a center ground patch 302 may be formed to connect all the ground vias in the center cluster. Connection lines 306 may be provided to link the center ground patch 302 with a ground plane 304. Although this prior art solution may alleviate the above-described ground flooding deficiencies to some extent, full flooding is not achieved due to spacing setup. The connection lines 306 may be too thin to support the large currents required for ground flooding. And several ground vias 308 still do not have sufficient contact to the ground plane 304.
In view of the foregoing, it would be desirable to provide a solution for power and ground flooding in multilayer circuit boards which overcomes the above-described inadequacies and shortcomings.